SELF-ALIGNED TI AND CO SILICIDES FOR HIGH-PERFORMANCE SUB-0.18 MU-M CMOS TECHNOLOGIES

An overview of the development of advanced Ti and Co self-aligned sili cide (SALICIDE) processes for deep-sub micron high performance CMOS te chnologies at Texas instruments is presented. SALICIDES are a key fact or for scaling of high-performance CMOS devices. They are used to lowe r sheet resistance of gate and source/drain regions, contact resistanc e and source/drain series resistance, increasing device performance an d lowering RC delays to allow faster operation. Their applicability to deep-sub-micron technologies is determined by the fundamental materia ls aspects controlling silicide phase formation and evolution, as well as process integration issues such as effect of subsequent processing steps on the silicide films or effects of silicide related process st eps on transistor characteristics. The main scaling issues for convent ional processes, high resistivity on narrow lines for Ti SALICIDE and high diode leakage on shallow junctions for Co SALICIDE, are addressed . Detailed kinetic studies of the high resistivity to low resistivity phase transformations (TiSi2 C49 to C54 and CoSi to CoSi2) and their d ependence on Linewidth and film thickness are presented. A nucleation density model is shown to account for the measured linewidth dependenc e and effect of pre-amorphization implants on the TiSi2 C49 to C54 tra nsformation and explain, as a result, narrow line sheet resistance. Th is overview covers studies on rapid thermal processing (RTP) for Ti an d for Co SALICIDE, pre-amorphization implants and Mo impurities which allowed the first demonstration of low resistivity Ti SALICIDE at 0.10 mu m gate lengths, as well as applications to sub-0.18 mu m CMOS tech nologies and integration issues. (C) 1998 Elsevier Science S.A. All ri ghts reserved.