AN ALGORITHM FOR CLOCK CYCLE SELECTION IN BEHAVIORAL SYNTHESIS

Most of the High Level Synthesis (HLS) tools proposed to date, carry o ut the synthesis process in clock cycles. This strategy may lead to im plementations with a low clock cycle utilization. This problem becomes more important when multicycling is considered. In order to overcome it, we propose determining the clock cycle period during HLS. The tech nique is based on the minimization of the slack time of the operations thus allowing better clock period selection.