LINEAR CMOS TRIODE TRANSCONDUCTOR FOR LOW-VOLTAGE APPLICATIONS

A linear transconductor is presented which uses transistors biased in the triode region. Based on the regulated-cascode technique for mainta ining the drain-source voltage of triode-biased transistors, the circu it offers an advantage in terms of a low supply requirement, resulting from the use of a shea-channel pMOS transistor for the gain stage. An alysis and design considerations for optimising the large-signal chara cteristic are described. The simulated TI-ID of the proposed circuit i s smaller than -56dB for differential input ranges up to 0.8V(peak) at 3V for the entire transconductance tuning range.