A 3-DIMENSIONAL, PHYSICALLY-BASED COMPACT MODEL FOR IC VDMOS TRANSISTORS

A three-dimensional VDMOS model has been derived and implemented in SP ICE. The model was developed and characterized for the square cell, re ctangular grid device layout for Motorola's SmarTMOS(TM) technologies. The model includes physical models for R-DSon over gate voltage, temp erature and cell number. It also includes accurate, scalable models fo r the gate-charge, including the voltage-varying gate-drain capacitanc e and the distributed effects of the buried layer and interconnect met al resistances on the total on-resistance of the device. This allows e fficient and accurate modeling of typical VDMOS layouts. (C) 1998 Else vier Science Ltd. All rights reserved.