PREDICTION AND MEASUREMENT OF TEMPERATURE-FIELDS IN SILICON-ON-INSULATOR ELECTRONIC-CIRCUITS

Field-effect transistors (FETs) in conventional electronic circuits ar e in contact with the high-thermal-conductivity substrate. In contrast , FETs in novel silicon-on-insulator (SOI) circuits are separated from the substrate by a thermally resistive silicon-dioxide layer The laye r improves the electrical performance of SOI circuits. But it impedes conduction cooling of transistors and interconnects, degrading circuit reliability, This work develops a technique for measuring the channel temperature of SOI FETs. Data agree well with the predictions of an a nalytical thermal model. The channel and interconnect temperatures dep end strongly on the device and silicon-dioxide layer thicknesses and t he channel-interconnect separation. This research facilitates the ther mal design of SOI FETs to improve circuit figures of merit, e.g., the median time to failure (MTF) of FET-interconnect contacts.