SYNTHESIS OF MVL FUNCTIONS USING INPUT AND OUTPUT ASSIGNMENTS

A number of decomposition based mapping techniques are proposed. In th ese techniques, the synthesis problem is formulated as a mapping from an input matrix to an output matrix. The minimisation is obtained by c onstructing a 'matching-count matrix'. The entries of the matching-cou nt matrix MCij represent the number of entry matches between the input variable number i in the input matrix (X) and the output function num ber j in the output matrix (Y). It then selects those input-output pai rings that give the maximum matching count, thus maximising the number of switching operations which can be eliminated in the realisation of multiple-valued logic (MVL) functions. The proposed techniques are cl assified as: output-phase with complement, input-phase with and withou t complement. Numerical results are presented to show that the propose d techniques result in significant reduction in the number of switchin g operators required for the implementation of 5000 randomly generated r-valued functions (for I = 3, 4 and 5). It is also shown that the in put-phase assignment techniques do not require any additional hardware circuitry at the output to restore the original function. This may gi ve this technique an edge over other techniques.