AN EVALUATION OF HARDWARE-BASED AND COMPILER-CONTROLLED OPTIMIZATIONSOF SNOOPING CACHE PROTOCOLS

Coherence misses and invalidation traffic limit the performance of bus -based multiprocessors using write-invalidate snooping caches. This pa per considers optimizations of a write-invalidate protocol that remove such overhead. While coherence misses are attacked by a hybrid update /invalidate protocol and another technique where update instructions a re selectively inserted by a compiler, invalidation traffic is reduced by three optimizations that coalesce ownership acquisition with miss handling: migrate-on-dirty, an adaptive hardware-based scheme, and com piler-controlled insertion of load-exclusive instructions. The relativ e effectiveness of these optimizations are evaluated using detailed ar chitectural simulations and a set of four parallel programs. We find t hat while both of the update-based schemes effectively remove most coh erence misses, the hybrid update/invalidate scheme causes lower traffi c. By contrast, the compiler-based approach to cut invalidation traffi c is slightly more efficient than the adaptive hardware-based scheme. Moreover, the migrate-on-dirty heuristic is found to have devastating effects on the miss rate. (C) 1998 Elsevier Science B.V.