SEQUENTIAL LOGIC OPTIMIZATION FOR LOW-POWER USING INPUT-DISABLING PRECOMPUTATION ARCHITECTURES

Precomputation is a recently proposed logic optimization technique whi ch selectively disables the inputs of a logic circuit, thereby reducin g switching activity and power dissipation, without changing logic fun ctionality. In sequential precomputation, output values required in a particular clock cycle are selectively precomputed one clock cycle ear lier, and the original logic circuit is ''turned off'' in the succeedi ng clock cycle. We target a general precomputation architecture for se quential logic circuits, and show that it is significantly more powerf ul than the architecture previously treated in the literature. The ver y power of this architecture makes the synthesis of precomputation log ic a challenging problem.We present a method to automatically synthesi ze precomputation logic for this architecture. Up to 66% reduction in power dissipation is possible using the proposed architecture. For man y examples, the proposed architecture result in significantly less pow er dissipation than previously developed methods.