AN INTEGRATED CALL ADMISSION AND BUFFER MANAGEMENT SCHEME FOR LAN INTERCONNECTION OVER A SHARED-MEMORY ATM SWITCH

We consider the problem of interconnecting low speed LANs over a high- speed shared-memory ATM switch. A bottleneck is formed when more than one source originate traffic to the same destination LAN. In this case , a congestion may be created at the output gateway (destination LAN i nterface) and the required services are interrupted. In this paper we propose a new integrated scheme for call admission (CAC) and buffer ma nagement. The objective of the scheme is to prevent the congestion at the destination LANs, as well as within the ATM switch, while minimizi ng connection rejection rates (maximizing the utilization of the ATM s witch). The scheme uses two types of parameters: first, the connection parameters which are estimated at the network interface unit and spec ified during connection set-up, and second, the actual traffic charact eristics and buffer requirements. Therefore, the proposed scheme combi nes both parameter-based and measurement-based approaches to the probl ems of call admission and congestion control. The proposed scheme is s hown not to require intensive computations and can be implemented in r eal time in a high-speed ATM switch. A simulation model for the system is developed from which the performance of our integrated CAC and buf fer management scheme is evaluated. It is shown that the application o f our CAC criteria maintains cell/packet dropping to within the same o rder of magnitude. It is also shown that using virtual buffer allocati on, in conjunction with our CAC criteria, results in almost no cell/pa cket dropping. (C) 1998 Elsevier Science B.V.