HIGH-SPEED AND LOW-COST REVERSE CONVERTERS FOR THE (2N-1,2N,2N+1) MODULI SET

In this brief, new architectures are presented for the conversion of r esidues to binary equivalents in the (2n-1, 2n, 2n+1) moduli set, Both of the architectures presented are based on a new algorithm, which el iminates a multiplication. In the design of the architectures, speed a nd cost are considered as the principal factors. The proposed architec tures use fewer multipliers and adders of smaller size. A comparison i n terms of hardware requirements, delay estimates, and complexity is m ade to establish the advantages of the proposed design.