EXPERIMENTAL STUDIES ON DEEP-SUBMICRON CMOS SCALING

N- and surface channel p-MOSFETs and CMOS ring oscillators with channe l lengths down to 0.2 mu m and physical gate oxide thicknesses of 2.5 nm-5.8 nm were fabricated. The parasitic SD series resistance, thresho ld voltages, finite thickness of inversion layer including quantum and polysilicon gate depletion effects, drain saturation current, load ca pacitance of ring oscillator and ring oscillator speed were characteri zed at voltages from 1.5 to 3.3 V. The results confirmed the accuracy of the analytical models recently developed. The existence of an optim um gate oxide for given V-gs V-th, R-s and L-eff is demonstrated from both the analytical model and the experimental data.