GENERIC VLSI ARCHITECTURE FOR BLOCK-MATCHING MOTION ESTIMATION ALGORITHMS

In this article, a generic VLSI architecture which is both programmabl e and scalable is proposed for block-matching motion estimation algori thms. Various motion estimation algorithms can be implemented using th e proposed architecture by organizing the individual search positions (checking points) into checking vectors. A checking vector is processe d in parallel by fully exploiting its data dependency. The optimal cho ice for the size of checking vector is discussed based on the design t radeoffs among processing speed, silicon area, and I/O bandwidth. Appr opriate designs are recommended for various video applications. (C) 19 98 John Wiley & Sons, Inc. Int J Imaging Syst Technol, 9, 267-273, 199 8.