A compensation circuit has been developed to reduce the V-BE wafer spr
ead of a bipolar transistor by taking advantage of the correlation bet
ween pinched base resistor R-P and I-S of the Ebers-Moll model. This c
ompensation circuit was used in the design of a Celsius temperature se
nsor with intrinsic reference, improving its accuracy at least five ti
mes within the 0 degrees C to 100 degrees C interval. Accuracy has bee
n calculated considering wafer level statistical modeling of bipolar I
C parameters, circuit sensitivity, and worst case circuit simulation.
This technological compensation procedure allows to obtain an accurate
IC temperature sensor without final trimming at wafer level. (C) 1998
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