A PHYSICAL MODEL FOR THE CORRELATION BETWEEN HOLDING VOLTAGE AND HOLDING CURRENT IN EPITAXIAL CMOS LATCH-UP

A new physical model concerning the holding points for latch-up in epi taxial CMOS structures is established by combining the lateral p-i-n h igh level injection and the vertical BJT base push-out formula. The mo del matches adequately the correlation between holding voltage and hol ding current extensively measured from different combinations of tempe ratures, epitaxial layer thicknesses, and anode-to-cathode spacings, T his is also the case for the two-dimensional device simulations. A qua ntitative analysis based on the model consistently judges the crucial role of the vertical BJT base push-out width in producing the observed correlation. The potential merits of the model in extended applicatio ns are outlined.