DESIGN-FOR-TESTABILITY FOR PATH DELAY FAULTS IN LARGE COMBINATIONAL-CIRCUITS USING TEST POINTS

We present a method for test-point insertion in large combinational ci rcuits, to increase their path delay fault testability, Using an appro priate test application scheme with multiple clock periods, a test poi nt on a line g divides the set of paths through g for testing purposes into a subset of paths from the primary inputs up to g. and a subset of paths from g to the primary outputs. Each one of these subsets can be tested separately. The number of paths that need to be tested direc tly is thus reduced. In addition, by breaking an untestable path into two or more testable subpaths, it is possible to obtain a fully testab le circuit, Test-point insertion is done to reduce the number of paths , using a time efficient procedure. Indirectly, it also reduces the nu mber of tests and renders untestable paths testable. When the number o f paths is sufficiently small, and if the test generation procedure to be used for the circuit is known, a procedure is given to perform tes t-point insertion directly targeting the path delay faults that are st ill untestable. Experimental results are presented to demonstrate the effectiveness of the proposed methods in increasing the testability of large benchmark circuits, and to demonstrate the overheads involved.