INTEGRATION OF LOW PERMITTIVITY DIELECTRIC IN AL DUAL DAMASCENE ARCHITECTURE FOR LOW PARASITIC ON-CHIP INTERCONNECT APPLICATIONS

Authors
ZHAO B FEILER D LIU QZ NGUYEN CH BRONGO M KUEI J RAMANATHAN V ZHANG H WU J RUMER M BIBERGER MA SACHAN V JAMES D
Citation
B. Zhao et al., INTEGRATION OF LOW PERMITTIVITY DIELECTRIC IN AL DUAL DAMASCENE ARCHITECTURE FOR LOW PARASITIC ON-CHIP INTERCONNECT APPLICATIONS, Electronics Letters, 34(13), 1998, pp. 1309-1310
Citations number
10
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Electronics Letters → ACNP
ISSN journal
00135194
Volume
34
Issue
13
Year of publication
1998
Pages
1309 - 1310
Database
ISI
SICI code
0013-5194(1998)34:13<1309:IOLPDI>2.0.ZU;2-O
Abstract
A low dielectric constant (low-kappa) material has been successfully i ntegrated in an Al dual damascene interconnect architecture where the low-kappa dielectric (kappa < 3) was used as the intra/inter level die lectric (ILD). In addition to a reduction in intra-level and inter-lev el capacitance, low via resistance, excellent electrical isolation, an d good reliability characteristics were observed.