ADDRESS GENERATION FOR MEMORIES CONTAINING MULTIPLE ARRAYS

We present techniques for generating addresses for memories containing multiple arrays. Because these techniques rely on the inversion or re arrangement of address bits, they are faster and require less hardware to compute than the traditional technique of addition. Use of these t echniques can improve performance and cost of application-specific mem ory subsystems by decreasing effective access time to arrays and by re ducing address generation hardware, The primary drawback to this appro ach is that extra memory space is occasionally required, but in over a million tested cases, this extra memory space is on average only 2% a nd no worse than 17.4 % of the utilized memory space, This amount of w asted address space is significantly less than the amount required by the only known similar technique [7] and rarely necessitates the alloc ation of additional memory components, These techniques provide a foun dation for adder-free address generation for manually and automaticall y generated application-specific memory designs.