LOT - LOGIC OPTIMIZATION WITH TESTABILITY - NEW TRANSFORMATIONS FOR LOGIC SYNTHESIS

A new approach to optimize multilevel logic circuits is introduced. Gi ven a multilevel circuit, the synthesis method optimizes its area whil e simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transfor mations involving EX-OR gates as well as Reed-Muller expansions have b een introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-patte rn testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than oth er similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx, Specifically fo r ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based t ransformations successfully contributed toward generating smaller circ uits compared to other state-of-the-art logic optimization tools.