A JOINT GATE SIZING AND BUFFER INSERTION METHOD FOR OPTIMIZING DELAY AND POWER IN CMOS AND BICMOS COMBINATIONAL LOGIC

This paper presents the first reported joint gate sizing and buffer in sertion method for minimizing the delay of power constrained combinati onal logic networks that can incorporate a mixture of unbuffered and b uffered gates (or mixture of CMOS and BiCMOS gates), In the method, bu ffered gates in a network are decided on by an iterative process that uses a sequence of sizing optimizations where after each sizing optimi zation an update to the selection of buffered gates is made. In this w ay, high drive capability buffered (i.e., BICMOS) gates with sufficien tly low fan-out are identified and replaced with a lower power unbuffe red (i.e., CMOS) version. As well, the optimality of the final design is assessed based on a lower-bound delay value that is calculated. Exp erimental results have confirmed the efficiency and utility of the pro posed method. In 8-b adder or 8 x 8 b multiplier networks, just two it erations are sufficient to achieve a delay that is at worst within 0.6 % of its final optimized value and at worst within 10% of the lower-bo und value. In the design of BiCMOS networks, it is seen that a speed a dvantage (at equivalent power) can be systematically achieved by using a mix of CMOS and BICMOS gates versus using all CMOS or all BICMOS ga tes and that this advantage increases with the tightness of the power constraint and with load capacitance.