PERFORMANCE OPTIMIZATION BY GATE SIZING AND PATH SENSITIZATION

In the circuit model where outputs are latched and input vectors are s uccessively applied at inputs, the gate resizing approach to reduce th e delay of the critical path may not improve the performance. Since th e clock period is determined by delays of both long and short paths in the combinational circuit, gates lying in sensitizable long and short paths can be selected for resizing. For feasible settings of the cloc k period, new algorithms and corresponding gate selection methods for resizing are proposed in this paper. Our algorithms are tested on ISCA S'85 benchmark circuits and experimental results show that the clock p eriod ran be optimized efficiently with our gate selection methods.