ASYNCHRONOUS COMPARISON-BASED DECODERS FOR DELAY-INSENSITIVE CODES

A comparison-based decoder detects the arrival of a code word by compa ring the received checkbits with the checkbits computed using the rece ived data. Implementation issues underlying comparison-based decoders for systematic delay-insensitive (DI) or unordered codes is the subjec t of this paper. We show that if the decoder is to be implemented usin g asynchronous logic, i.e., if the gate and wire delays are arbitrary (unbounded but finite), then it is impossible to design a comparison-b ased decoder for any code that is more efficient than a dual-rail code . In other words, the encoded word must contain at least twice as many bits as the data. In addition. the codes should satisfy two other pro perties, called the initial condition and the all-zero lower triangle (AZLT) property, for the realization of a delay-insensitive comparison -based decoder. The paper shows that comparison-based decoders for cod es that have the requisite level of redundancy and that satisfy the tw o properties can be implemented using asynchronous logic.