THE DESIGN OF AN ADAPTIVE ONLINE BINARY ARITHMETIC-CODING CHIP

In this paper, we present a very large scale integration (VLSI) design of the adaptive binary arithmetic coding for lossless data compressio n and decompression. The main modules of it consist of an adaptive pro bability estimation modeler (APEM), an arithmetic operation unit (AOU) , and a normalization unit (NU), A new bit-stuffing technique, which s imultaneously solves both the carry-over and source-termination proble ms efficiently, is proposed and designed in an NU, The APEM estimates the conditional probabilities of input symbols efficiently using a tab le lookup approach with 1.28-kbytes memory. A new formula which effici ently reflects the change of symbols' occurring probability is propose d, and a complete binary tree is used to set up the values in the prob ability table of an APEM, In an AOU, a simplified parallel multiplier, which requires approximately half of the area of a standard parallel multiplier while maintaining a good compression ratio, is proposed. Ow ing to these novel designs, the designed chip can compress any type of data with an efficient compression ratio. An asynchronous interface c ircuit with an 8-b first-in first-out (FIFO) buffer for input/output ( I/O) communication of the chip is also designed. Thus, both I/O and co mpression operations in the chip can be done simultaneously. Moreover, the concept of design for testability is used and a scan path is impl emented in the chip. A prototype 0.8-mu m chip has been designed and f abricated in a reasonable die size. This chip can yield a processing r ate of 3 Mb/s with a clock rate of 25 MHz.