HIGH-LEVEL SYNTHESIS FOR WEAKLY TESTABLE DATA PATHS

We present a high-level synthesis scheme that considers weak testabili ty of generated register-transfer level (RTL) data paths, as well as t heir area and performance. The weak testability, proposed in our previ ous work, is a testability measure of RTL data paths for non-scan desi gn. In our scheme, we first extract a condition on resource sharing su fficient for weak testability from a data flow graph before synthesis, and treat the condition as design objectives in the following synthes is tasks. We propose heuristic synthesis algorithms which optimize are a and the design objectives under the performance constraint.