PARTIAL SCAN DESIGN METHODS BASED ON N-FOLD LINE-UP STRUCTURES AND THE STATE JUSTIFICATION OF PURE LOAD HOLD FLIP-FLOPS/

We will present a partial scan design method based on n-fold line-up s tructures in order to achieve high fault efficiency and reduce test pa ttern generation time for practical LSIs. We will also present a parti al scan design method based on the state justification of pure load/ho ld FFs in order to achieve high fault efficiency and reduce the number of scan FFs for practical LSIs with lots of load/hold FFs. Experiment al results for practical LSIs show that our presented methods can achi eve high fault efficiency (more than 99%) and reduce the number of sca n FFs for the LSI with lots of load/hold FFs.