ON ACCELERATION OF LEST POINTS SELECTION FOR SCAN-BASED BIST

This paper presents an acceleration of test points selection for circu its designed by a full-scan based BIST scheme. In order to accelerate the test points selection based on cost minimization, and reflecting r andom pattern testability, we introduce three techniques, the simultan eous selection of plural test points, the simplified selection of test points by the cost reduction factor, and the reduction of the number of test point candidates. We implement a program based on the proposed techniques and evaluate its efficiency experimentally using large sca le circuits (26 k-420 k gates).