TRANSISTOR LEAKAGE FAULT-DIAGNOSIS FOR CMOS CIRCUITS

This paper presents a new methodology for diagnosing transistor leakag e faults in a CMOS circuit by using both I-DDQ and logic value informa tion. A hierarchical procedure is used to identify and delete impossib le fault candidates efficiently and a procedure is employed to generat e diagnostic tests for improving diagnostic resolution. A novel approa ch for handling the intermediate output voltage of a faulty gate is us ed in new methods for fault simulation and diagnostic test generation based on primary output values. Experimental results on ISCAS'85 circu its show the effectiveness of the proposed methodology.