LOGIC OPTIMIZATION - REDUNDANCY ADDITION AND REMOVAL USING IMPLICATION RELATIONS

The logic optimization based on redundancy addition and removal is one of methods which can deal with large-scale logic circuits. In this lo gic optimization a few redundant elements are added to a logic circuit , and then many other redundant elements which are generated by the re dundancy addition are identified and removed. In this paper an optimiz ation method based on redundancy addition and removal using implicatio n relations is proposed. The advantage of the proposed method is to id entify removable redundant elements with short time, because the propo sed method directly identifies redundant elements using implication re lations from two illegal signal assignments which are produced by redu ndancy addition. The experimental results compared this method with an other method show that this method is faster than the another method w ithout declining the optimization ability.