GUIDED-PROBE DIAGNOSIS OF LSIS CONTAINING MACROCELLS

A novel method for the guided-probe diagnosis of high-performance LSIs containing macrocells, which have no internal netlist essential to th e diagnosis, has been developed. In this method, the macrocell netlist is derived from its layout by extracting a leaf-cell-level netlist an d is combined with the original one. Logic models for the leaf cells i n the extracted netlist are also generated to obtain the logic-simulat ion data in the macrocells. The logic modeling is extended for applica tion to memory macrocells, based on the idea that analog-behavior leaf cells in the memory macrocells are converted into logically equivalen t circuits for logic simulation. Specifically, sense amplifiers and wi red-or connections on bit lines are replaced with the corresponding lo gic-behavior models. The proposed method has been successfully applied to actual design data of LSIs containing macrocells, and it has been verified that it enables fault paths inside macrocells to be accuratel y traced and that the logic models give good timing resolution in the logic simulation. Using the proposed method, LSIs containing macrocell s will be able to be diagnosed regardless of the macrocell types, with out the need for a ''golden'' device, by an electron-beam guided probe system.