EFFICIENT TIMING ANALYSIS FOR CMOS CIRCUITS CONSIDERING DATA DEPENDENT DELAYS

Both long- and short-path delays are used to determine the valid clock ing for various complementary metal-organic-semiconductor (CMOS) circu its such as single phase latching, asynchronous, and wave pipelining, Therefore, accurate estimation of both long and short-path delays is v ery crucial In the designing and testing of high speed CMOS circuits, Most of the previous approaches in detecting long and short sensitizab le paths assume that the rising and falling of gate delays are either fixed or bounded, In fact the gate delay of CMOS circuits may also dep end on how many and which inputs are rising or falling and the arrival times of those rising or falling inputs, For instance, the delay for a two-input CMOS NAND gate may vary as much as a factor of two based o n whether one input or two inputs are changing. We shall refer a gate delay model which considers these factors as data dependent delay mode l. Gray st al. have proposed an approach based on simulation with even t pruning to deal with this type of delay model [1]. In this paper, we propose several algorithms to compute the longest and shortest sensit izable path delays based on a data dependent delay model. A proposed a lgorithm which is based on a combination of modified static (topologic al) timing analysis and path sensitization techniques seems to offer t he best performance. The results obtained have shown to be more accura te than the traditional path sensitization approach based on bounded d elay model.