ELECTRICAL MODELING AND SIMULATION CHALLENGES IN CHIP-PACKAGE CODESIGN

Authors
Citation
Ac. Cangellaris, ELECTRICAL MODELING AND SIMULATION CHALLENGES IN CHIP-PACKAGE CODESIGN, IEEE MICRO, 18(4), 1998, pp. 50-59
Citations number
11
Categorie Soggetti
Computer Science Hardware & Architecture","Computer Science Software Graphycs Programming","Computer Science Hardware & Architecture","Computer Science Software Graphycs Programming
Journal title
ISSN journal
02721732
Volume
18
Issue
4
Year of publication
1998
Pages
50 - 59
Database
ISI
SICI code
0272-1732(1998)18:4<50:EMASCI>2.0.ZU;2-1
Abstract
High-performance, multifunctional systems demand novel, often revoluti onary, practices in functional-block integration and packaging. Indepe ndent chip, package, and board design will have to give way to a holis tic approach.