DESIGN TECHNIQUES FOR A LOW-POWER LOW-COST CMOS A D CONVERTER/

A 10 bit 200 kHz algorithmic analog-to-digital converter (ADC) was des igned to demonstrate design techniques for low-power low-cost CMOS int egrated systems. A switched-bias power-reduction technique reduces the total system power by 40%, A layout technique employing extra thin po ly-layer lines instead of conventional dummy devices reduces plasma-in duced comparator offsets. Based on a standard digital CMOS process wit h a single poly layer, the ADC adopts metal-to-metal capacitors for in ternal charge storage. The experimental ADC was fabricated in a 0.6 mu m single-poly double-metal n-well CMOS technology, and showed a power consumption of 7 mW and a signal-to-noise-and-distortion ratio (SNDR) of 53 dB at the Nyquist sampling rate with a 3.3 V single supply volt age. The measured differential and integral nonlinearities of the prot otype are less than +/-0.8 and +/-1.8 LSB, respectively.