A 1.3-GHZ SOI CMOS TEST CHIP FOR LOW-POWER HIGH-SPEED PULSE PROCESSING

A test chip has been fabricated in a fully depleted SOI CMOS process w ith 0.25-mu m drawn gate length. It successfully demonstrates the type s of circuits required to perform digital filtering, detection, and da ta thinning functions at high clock speeds. The test chip contains ove r 5000 transistors and was clocked at speeds up to 1.3 GHz. A target a pplication for these circuits is a very wideband compressive receiver for;realtime spectral analysis, which requires digital signal processi ng to be performed on a 20-Gb/s data stream formed by digitizing a str eam of fast analog pulses. Adjustable high-speed on-chip clocks, input and output registers, and large decoupling capacitors allowed testing of the chip to be performed using an inexpensive, low-speed probe car d and a standard wafer prober.