FPGA ARCHITECTURES AS DEVICE-FLEXIBLE MACROS

An FPGA (field programmable gate array) architecture that can be reali zed as a macro on any type of device is described. Various products us e FPGAs among their components; however, they use them in combination with other LSIs (Such as custom designed LSIs). The aim of our macro-t ype FPGA architecture is to provide the means for creating programmabl e regions of any size and shape, on any type of device, and finally, t o combine the traditional multi-LSI systems into one chip. To make our architecture device independent, inside the logic cells, we simplifie d the structure of the logic component and separated it from the progr am memory. Since the logic cells are designed as minimum units of the macro, programmable regions of any size and shape can be easily achiev ed by placing the desired number of logic cells in the desired configu ration. The details of our architecture were determined through experi ments. As a sample realization, we implemented our architecture on a t hree metal layer CMOS SOG (sea of gates) gate array. (C) 1998 Scripta Technica.