A LOW-POWER-CONSUMPTION ARCHITECTURE FOR EMBEDDED PROCESSORS

This paper discusses a low-power-consumption architecture for the proc essor based on object code compression, especially the application of the idea to embedded processors. In the proposed method, duplicated in structions are unified to compress the program. An instruction decompr ession circuit is added, which reorganizes the object code from the ps eudocode generated by the compression. The instruction decompression c ircuit and the processor are integrated into a single chip, which help s to reduce the bandwidth needed in the interface to the external memo ry. Then, the power consumption is reduced greatly. As a result of exp eriments, when the proposed method is applied to the ARM610 32-bit RIS C processor, the code is compressed by 62.5%. The power consumption in the instruction memory is reduced by 42.3%. The area of the instructi on decompression circuit that is additionally implemented is 0.983 mm (2). (C) 1998 Scripta Technica, Electron Comm Jpn Pt 3, 81(10): 83-90, 1998.