STACKED HIGH-EPSILON GATE DIELECTRIC FOR GIGASCALE INTEGRATION OF METAL-OXIDE-SEMICONDUCTOR TECHNOLOGIES

Advances in lithography and thinner SiO2 gate oxides have enabled the scaling of metal-oxide-semiconductor technologies to sub-0.25 mu m fea ture size. A major hurdle in the gale dielectric scaling using convent ional thermally grown SiO2 has been excessive tunneling that occurs in ultrathin (<25 Angstrom) SiO2. High dielectric constant materials suc h as Ta2O5 have been suggested as a substitute for SiO2. However, thes e materials have high concentrations of bulk fixed charge, unacceptabl e levels of Si-Ta2O5 interface trap states, and low silicon interface carrier mobilities. This letter summerizes an elegant solution to thes e issues through synthesis of a thermally grown SiO2(15 Angstrom)-Ta2O 5(30 Angstrom)-SiO2(5-10 Angstrom) dielectric with improvements in lea kage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit exc ellent subthreshold, saturation, and drive currents.