PROSPECTS OF DISTRIBUTED SHARED-MEMORY FOR REDUCING GLOBAL TRAFFIC INSHARED-BUS MULTIPROCESSORS

As an effort, not a mutually exclusive but rather complementary to dev eloping better backplane bus, this paper considers adapting distribute d shared-memory (DSM) architectures to improve traditional shared-bus designs. We consider two well-known DSM architectures, namely Cache-co herent Non-Uniform Memory Architecture (NUMA) and Cache-Only Memory Ar chitecture (COMA), in reducing bus traffic. Our study shows that COMA provides excellent opportunity of significantly reducing bandwidth req uirement for the bus while cache-coherent NUMA provides a marginal imp rovement.