P-N-JUNCTION PERIPHERAL CURRENT ANALYSIS USING GATED DIODE MEASUREMENTS

A modified method for analysis of the current-voltage characteristics of a gated diode structure is proposed and validated in order to inves tigate the peripheral reverse current in a silicon p-n junction diode. The peripheral generation current in modern p-n diodes is attributed fully to surface generation underneath the thick field oxide surroundi ng the structure, which typically contains a high density of interface traps. For a gated diode structure, the current region observed for l arge gate voltages, VG, is linked to the generation associated with th e depletion at the Si-thick SiO2 interface. It will be shown that, com pared to the classical analysis, this current step is a better alterna tive to assess the peripheral generation. The 25 times higher sensitiv ity of gated diode measurements in this mode allows one to reduce the test device perimeter and dimensions, without penalizing the measureme nt resolution for interface states. The main advantage of the proposed method is related to the fact that for the peripheral current extract ion, only the measurement of one diode is needed instead of the tediou s measurements and analyses of a set of diodes. (C) 1998 American Inst itute of Physics.