THEORY AND DESIGN OF CMOS HSTL I O PADS

Authors
ESCH GL MANLEY RB
Citation
Gl. Esch et Rb. Manley, THEORY AND DESIGN OF CMOS HSTL I O PADS, HEWLETT-PAC, 49(3), 1998, pp. 46-52
Citations number
4
Categorie Soggetti
Engineering, Eletrical & Electronic","Instument & Instrumentation","Computer Science Hardware & Architecture
Journal title
HEWLETT-PACKARD JOURNAL
ISSN journal
00181153 → ACNP
Volume
49
Issue
3
Year of publication
1998
Pages
46 - 52
Database
ISI
SICI code
0018-1153(1998)49:3<46:TADOCH>2.0.ZU;2-I
Abstract
To control reflections, the impedance of integrated circuit output pad drivers must be matched to the impedance of the transmission lines to which the pads are connected. HP's HSTL (high-speed transceiver logic ) controlled impedance I/O pads use an on-chip impedance matching netw ork that compensates for process, voltage, and temperature (PVT) varia tions.