IMPLEMENTATION OF A HIGH-SPEED FAST FOURIER-TRANSFORM VLSI CHIP

Very high speed processing of radar signals has led to the requirement of very high speed conversion of signals from the time domain to the frequency domain. In this paper we discuss the implementation of an FF T chip based on the proposed digit slicing architecture. The paper beg ins with a discussion of the digit slicing technique. This is followed by discussions on the basic building blocks of the digit slicing FFT and implementation of a prototype digit slicing FFT using DSP station. The paper is concluded by comparing the speed and other properties of the unsliced FFT and digit slicing FFT architectures. (C) 1998 Publis hed by Elsevier Science Ltd. All rights reserved.