DEFECT TOLERANCE IN VLSI CIRCUITS - TECHNIQUES AND YIELD ANALYSIS

Current very-large-scale-integration (VLSI) technology allows the manu facture of large-area integrated circuits with submicrometer feature s izes, enabling designs with several millions of devices. However; impe rfections in the fabrication process result in yield-reducing manufact uring defects, whose severity grows proportionally with the size and d ensity of the chip. Consequently, the development and use of yield-enh ancement techniques at the design stage, to complement existing effort s at the manufacturing stage, is economically justifiable. Design-stag e yield-enhancement techniques are aimed at making the integrated circ uit ''defect tolerant,'' i.e., less sensitive to manufacturing defects . They include incorporating redundancy into the design, modifying the circuit floorplan, and modifying its layout. Successful designs of de fect-tolerant chips must rely on accurate yield projections. This pape r reviews the currently used statistical yield-prediction models and t heir application to defect-tolerant designs. We then provide a detaile d survey of various yield-enhancement techniques and illustrate their use by describing the design of several representative defect-tolerant VLSI circuits.