PERFORMANCE EVALUATION OF HIGH-SPEED NETWORK PROTOCOLS BY EMULATION ON A VERSATILE ARCHITECTURE

The goal of this study is to validate a new simulation technique for p erformance evaluation of discrete lime queuing networks. This techniqu e uses a versatile architecture, which has changed from its primary pu rpose : circuit emulation in the design flow of chips. It is shown tha t this technique can be used to highlight rare events, such as realist ic packet loss probability in high-speed switched networks. (C) Elsevi er, Paris.