DESIGN AND IMPLEMENTATION OF THE STAR EXPERIMENTS DAQ

The STAR experiment is one of the two large detectors currently being built at the Relativistic Heavy Ion Collider (RHIC) at Brookhaven Nati onal Laboratory, Upton, U.S.A. The major issue of STAR's DAQ is the la rge amount of data that has to be processed as fast as possible. The r equired data rate is of the order of 90 Gbits/s which has to be proces sed and scaled down to about 15 MBytes/s and stored to tape or other p ermanent archiving media. To be able to do so the STAR DAQ uses a cust om built ASIC which preprocesses the raw data for later use by a softw are Level 3 trigger. The Level 3 trigger selects events to be archived depending on physics criteria based upon the particle track informati on extracted during Level 3 processing. The design presented is a mass ively parallel multiprocessor system which consists of front end micro processors hierarchically organized within a VME crate system. Each VM E crate contains 6 custom made Receiver Boards with 3 Intel I960HD pro cessors per board for a total of 18 processors per crate. The STAR's T PC detector uses 24 such crates and the SVT detector will use 4 crates for a total of 504 microprocessors.