DERIVING LOGIC SYSTEMS FOR PATH DELAY TEST-GENERATION

We present an algorithm to derive logic systems for various classes of path delay test problems. In these logic systems, the value of a sign al represents the relevant conditions that occur during a set of conse cutively applied vectors. Starting from a set of basic values for vali d signals at primary inputs, a state transition graph is constructed t o enumerate all possible signal states relevant to path activation tha t are reachable by Boolean operations. These states include all incomp letely specified states, composed as combinations of basic values. A d istinguishability analysis then finds all state-pairs that need to be distinguished during test generation. The final step minimizes the num ber of states. For forward and backward implications of test generatio n in combinational or sequential circuits, the procedure provides opti mal logic systems. We define optimality as the smallest set of logic s tates that provides the least possible ambiguity in implications. Thus , an optimal set of logic states will minimize the number of backtrack s in test generation. A 10-valued logic described in the literature is found to be optimal for generating tests for single path delay faults . Other problems addressed in this paper include compact test generati on through activation of many single path delay faults, test generatio n for rated-clock test application, and test generation for multiple p ath delay faults. The limitations and capabilities of various logic sy stems are illustrated by examples.