DESIGN OF CACHE TEST HARDWARE ON THE HP PA8500

Authors
BRAUCH J FLEISCHMAN J
Citation
J. Brauch et J. Fleischman, DESIGN OF CACHE TEST HARDWARE ON THE HP PA8500, IEEE design & test of computers, 15(3), 1998, pp. 58-63
Citations number
8
Categorie Soggetti
Computer Science Hardware & Architecture","Computer Science Hardware & Architecture
Journal title
IEEE design & test of computers → ACNP
ISSN journal
07407475
Volume
15
Issue
3
Year of publication
1998
Pages
58 - 63
Database
ISI
SICI code
0740-7475(1998)15:3<58:DOCTHO>2.0.ZU;2-5
Abstract
Refinements to testing strategies for earlier microprocessor on-chip c aches led to fast, efficient characterization and debugging of the sma ller geometry PA8500 cache.