A PARALLEL ASIC ARCHITECTURE FOR EFFICIENT FRACTAL IMAGE-CODING

Fractal image coding is a compression technique with many promising fe atures, but it has been primarily placed in the class of archival codi ng algorithms due to its computationally expensive encoding algorithm. Though fractal coding has been extensively optimized for speed, it is still not practical for real-time applications on most sequential mac hines. The problem with fractal coding lies in the large amount of pix el block comparisons that are required, which makes fractal coding bet ter suited toward parallel systems. At the same time, VLSI area has be come a much less important constraint in chip design due to better fab rication techniques and smaller micron technologies. This has lead to a recent trend for designing parallel subsystems and including multime dia ASIC circuitry on general purpose CPUs. In this paper, we will pre sent a parallel ASIC array architecture for use in fractal encoding th at performs a full domain quad-tree search in near real-time for stand ard sized gray scale images. The design is also scalable so that large r images can be encoded faster by adding chips to the array. In design ing this architecture, we include novel optimizations at the algorithm ic, architecture, and circuit levels.