AN IMPLEMENTATION APPROACH OF THE IEEE-1149.1 FOR THE ROUTING TEST OFA VLSI MASSIVELY-PARALLEL ARCHITECTURE

This paper presents an implementation approach for the test of routers in a fine grain massively parallel architecture. First, an ad hoc tes t technique which diffuses test messages router by router is analyzed. Even though the technique does not add hardware, it is shown ineffici ent and not applicable due to practical constraints such as the limite d number of pins of the chip implementing the machine. Based on a hier archical implementation of the IEEE 1149.1 standard, two approaches ar e proposed and compared in terms of the area overhead, the overall tes t time and the flexibility in applying tests and diagnosing the router s inside the machine. The basic idea for both approaches is to constru ct groups of basic cells which are driven by the same test block and c ompare their test results after the same test vectors are applied at e ach cell input. The two approaches differ in the granularity of a basi c cell. The choice of an implementation approach is not trivial. It is shown that each approach presents better performance than the other, that is, the approach which allows better fault coverage and less test time requires more silicon and less diagnostic possibilities compared to the second approach.