STATISTICAL DELAY-FAULT COVERAGE ESTIMATION FOR SYNCHRONOUS SEQUENTIAL-CIRCUITS

We present a technique to statistically estimate path-delay fault cove rage for synchronous sequential circuits. We perform fault-free simula tion using a multivalue algebra and accumulate signal transition stati stics, from which we calculate controllabilities of all signals and se nsitization probabilities for all gates and flip-flops. We use a rated clock testing model where all time frames operate at the rated clock. We obtain path observabilities either by enumerating paths in the all -paths method, or by a nonenumerative method considering only the long est paths. The path-delay fault detectability is the product of observ abilities of signals on paths from primary inputs (Pls) or pseudo-prim ary inputs (PPIs) to primary outputs (POs) or pseudo-primary outputs ( PPOs), and the controllability on the corresponding PI or PPI. We use the optimistic update rule of Bose et al, for updating latches during logic simulation. When compared with exact fault simulation, the avera ge absolute deviation in our statistical fault coverage estimation tec hnique is 1.23% and the very worst absolute deviation was 6.59%. On av erage, our method accelerates delay fault coverage computation four ti mes over an exact path delay fault simulator.