MONTE-CARLO OPTIMIZATION OF SUPERCONDUCTING COMPLEMENTARY OUTPUT SWITCHING LOGIC-CIRCUITS

The authors have previously proposed a new superconducting voltage-sta te logic family called complementary output switching logic (COSL), Th is logic family has been designed using a Monte Carlo optimization pro cess such that circuits have a high theoretical yield at 5-10 Gb/s clo ck speeds in spite of existing Josephson process variations. In the pr esent work the Monte Carlo optimization process is described and theor etical yields are calculated for the COSL 2- and 3-bit encoder circuit s. The circuit simulations use 5-10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are co mpared to modified variable threshold logic (MVTL) circuits and demons trate that COSL circuits should have a significantly higher theoretica l yield than MVTL at 10 Gb/s, Design rules for optimal COSL circuit la youts are also given, and experimental data are presented for 2-bit en coder circuits operating at multigigahertz clock frequencies. HSPICE i s used for all Monte Carlo simulations and the Josephson junction mode l is given in the Appendix.