DESIGN OF ATM AAL1 SAR FOR CIRCUIT EMULATION

The asynchronous transfer mode (ATM) adaptation layer type 1 (AAL1) se gmentation and reassembly (SAR) are designed and implemented by the he ld programmable gate array (FPGA). The SAR header is generated and pro cessed in the FPGA and the SAR payload is stored in an external first- in-first-out (FIFO) device. A method to recover the source clock, call ed synchronous residual time stamp (SRTS), is implemented. The designe d AAL1 SAR FPGA is properly tested in a prototype circuit board.