VIDEO SPEED LOW TOTAL VOLTAGE MATRIX ADDRESSING TECHNIQUE FOR SSFLC DISPLAYS

Authors
BECCHERELLI R FERRARA V DALESSANDRO A CAMPOLI F MALTESE P
Citation
R. Beccherelli et al., VIDEO SPEED LOW TOTAL VOLTAGE MATRIX ADDRESSING TECHNIQUE FOR SSFLC DISPLAYS, Ferroelectrics (Print), 214(1-2), 1998, pp. 701-708
Citations number
10
Categorie Soggetti
Physics, Condensed Matter","Material Science
Journal title
Ferroelectrics (Print) → ACNP
ISSN journal
00150193
Volume
214
Issue
1-2
Year of publication
1998
Pages
701 - 708
Database
ISI
SICI code
0015-0193(1998)214:1-2<701:VSLTVM>2.0.ZU;2-O
Abstract
Novel computed and experimental results are achieved with addressing m odes capable of video rate speed with equal selection and data voltage s and a commercially available FLC mixtures. Total voltage requirement s for integrated circuit drivers is strongly reduced and is now made c ompatible with existing STN driver technology. A new automatic fit pro cedure, necessary for fast evaluation of cell parameter and subsequent simulation of cell behavior under matrix addressing, is also describe d.